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arXiv · 0710.4722

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

Yu-Tsun Chien·Dong Chen·Jea-Hong Lou·Gin-Kou Ma·Rob A. Rutenbar·Tamal Mukherjee
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Abstract

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 $μ$m CMOS process.

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Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee. 2007-10-25. Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. https://arxiv.org/abs/0710.4722

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