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arXiv · 0710.4759

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

J. L. Rossello·V. Canals·S. A. Bota·A. Keshavarzi·J. Segura
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Abstract

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12mm technology showing excellent results.

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J. L. Rossello, V. Canals, S. A. Bota, A. Keshavarzi, J. Segura. 2007-10-25. A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. https://arxiv.org/abs/0710.4759

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