Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

D. C. Keezer; C. Gray; A. Majid; N. Taher

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arXiv · 0710.4761

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

D. C. Keezer·C. Gray·A. Majid·N. Taher

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Abstract

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about $\pm$25ps timing accuracy.

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BibTeX RIS

D. C. Keezer, C. Gray, A. Majid, N. Taher. 2007-10-25. Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. https://arxiv.org/abs/0710.4761

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