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arXiv · 1004.1741

Efficient multicore-aware parallelization strategies for iterative stencil computations

Jan Treibig·Gerhard Wellein·Georg Hager
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Abstract

Stencil computations consume a major part of runtime in many scientific simulation codes. As prototypes for this class of algorithms we consider the iterative Jacobi and Gauss-Seidel smoothers and aim at highly efficient parallel implementations for cache-based multicore architectures. Temporal cache blocking is a known advanced optimization technique, which can reduce the pressure on the memory bus significantly. We apply and refine this optimization for a recently presented temporal blocking strategy designed to explicitly utilize multicore characteristics. Especially for the case of Gauss-Seidel smoothers we show that simultaneous multi-threading (SMT) can yield substantial performance improvements for our optimized algorithm.

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Jan Treibig, Gerhard Wellein, Georg Hager. 2010-04-10. Efficient multicore-aware parallelization strategies for iterative stencil computations. https://doi.org/10.1016/j.jocs.2011.01.010

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