On the Simulation of Time-Triggered Systems on a Chip with BIP

Jan Olaf Blech; Benoit Boyer; Thanh Hung Nguyen

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arXiv · 1109.5505

On the Simulation of Time-Triggered Systems on a Chip with BIP

Jan Olaf Blech·Benoit Boyer·Thanh Hung Nguyen

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Abstract

In this report, we present functional models for software and hardware components of Time-Triggered Systems on a Chip (TTSoC). These are modeled in the asynchronous component based language BIP. We demonstrate the usability of our components for simulation of software which is developed for the TTSoC. Our software comprises services and an application part. Our approach allows us to simulate and validate aspects of the software system at an early stage in the development process and without the need to have the TTSoC hardware at hand.

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Jan Olaf Blech, Benoit Boyer, Thanh Hung Nguyen. 2011-09-26. On the Simulation of Time-Triggered Systems on a Chip with BIP. https://arxiv.org/abs/1109.5505

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