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arXiv · 1110.3655

Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System

Jorge Luiz e Silva·Joelmir Jose Lopes·Bruno de Abreu Silva·Antonio Carlos Fernandes da Silva
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Abstract

In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The results of benchmarks implemented using the static dataflow architecture are reported at the end of this paper.

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Jorge Luiz e Silva, Joelmir Jose Lopes, Bruno de Abreu Silva, Antonio Carlos Fernandes da Silva. 2011-10-17. Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System. https://arxiv.org/abs/1110.3655

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