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arXiv · 1203.4150

Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip

Ahmed H. M. Soliman·E. M. Saad·M. El-Bably·Hesham M. A. M. Keshk
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Abstract

The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Application Specific Integrated Circuits (ASICs), however, the fabrication process costs a lot. Implementing a NoC on an FPGA does not only reduce the cost but also decreases programming and verification cycles. In this paper, an Asynchronous NoC has been implemented on a SPARTAN-3E\textregistered device. The NoC supports basic transactions of both widely used on-chip interconnection standards, the Open Core Protocol (OCP) and the WISHBONE Protocol. Although, FPGA devices are synchronous in nature, it has been shown that they can be used to prototype a Global Asynchronous Local Synchronous (GALS) systems, comprising an Asynchronous NoC connecting IP cores operating in different clock domains.

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Ahmed H. M. Soliman, E. M. Saad, M. El-Bably, Hesham M. A. M. Keshk. 2012-03-19. Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip. https://arxiv.org/abs/1203.4150

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