Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

Hooman Jarollahi; Richard F. Hobson

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arXiv · 1302.4464

Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC

Hooman Jarollahi·Richard F. Hobson

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Abstract

This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and low-power portable devices. The proposed SRAM cell features ~13% area reduction compared to a conventional 6T cell, and features a unique bit-line and negative supply voltage biasing methodology and ground control architecture to enhance performance, and suppress standby leakage power.

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BibTeX RIS

Hooman Jarollahi, Richard F. Hobson. 2013-02-18. Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC. https://arxiv.org/abs/1302.4464

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