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arXiv · 1304.6672

Hardware Implementation of Algorithm for Cryptanalysis

Harshali Zodpe·Prakash Wani·Rakesh Mehta
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Abstract

Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays, building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.

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Harshali Zodpe, Prakash Wani, Rakesh Mehta. 2013-04-11. Hardware Implementation of Algorithm for Cryptanalysis. https://doi.org/10.5121/ijcis.2013.3102

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