Design and considerations of ADC0808 as interleaved ADCs

Abstract

Here in this paper we are presenting a digital system background technique for correcting the time offset error rate and gain mismatches in a time interleaved analog to digital converter system for N channel communication using 8 bit ADC0808 ICs. A time interleaved A to D converter system is an effective way to implement a high sampling rate ADC with relatively slow circuits. This paper analyses the benefits and derives an upper band on the performance by considering kT/C noise and slewing requirement of the circuit driving the system. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. A timing mismatch calibration technique is proposed that covers linear and non linear channel mismatches, unifies, and extends the channel models. A novel foreground channel mismatch identification method has been developed, which can be used to fully characterize dynamic linear mismatches. A background identification method provides accurate timing mismatch estimates.