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arXiv · 1409.7166

An Efficient Topology-Based Algorithm for Transient Analysis of Power Grid

Jim Jing-Yan Wang·Lan Yang·Jingbin Wang·Lorenzo Azevedo
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Abstract

In the design flow of integrated circuits, chip-level verification is an important step that sanity checks the performance is as expected. Power grid verification is one of the most expensive and time-consuming steps of chip-level verification, due to its extremely large size. Efficient power grid analysis technology is highly demanded as it saves computing resources and enables faster iteration. In this paper, a topology-base power grid transient analysis algorithm is proposed. Nodal analysis is adopted to analyze the topology which is mathematically equivalent to iteratively solving a positive semi-definite linear equation. The convergence of the method is proved.

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Jim Jing-Yan Wang, Lan Yang, Jingbin Wang, Lorenzo Azevedo. 2014-09-25. An Efficient Topology-Based Algorithm for Transient Analysis of Power Grid. https://arxiv.org/abs/1409.7166

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