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arXiv · 1505.06459

A Proof of Correctness for the Tardis Cache Coherence Protocol

Xiangyao Yu·Muralidaran Vijayaraghavan·Srinivas Devadas
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Abstract

We prove the correctness of a recently-proposed cache coherence protocol, Tardis, which is simple, yet scalable to high processor counts, because it only requires O(logN) storage per cacheline for an N-processor system. We prove that Tardis follows the sequential consistency model and is both deadlock- and livelock-free. Our proof is based on simple and intuitive invariants of the system and thus applies to any system scale and many variants of Tardis.

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Xiangyao Yu, Muralidaran Vijayaraghavan, Srinivas Devadas. 2015-05-24. A Proof of Correctness for the Tardis Cache Coherence Protocol. https://arxiv.org/abs/1505.06459

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