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arXiv · 1506.03193

Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems

Mohammad Shihabul Haque·Ang Li·Akash Kumar·Qingsong Wei
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Abstract

In this article, we propose a technique to accelerate nonvolatile or hybrid of volatile and nonvolatile processor cache design space exploration for application specific embedded systems. Utilizing a novel cache behavior modeling equation and a new accurate cache miss prediction mechanism, our proposed technique can accelerate NVM or hybrid FIFO processor cache design space exploration for SPEC CPU 2000 applications up to 249 times compared to the conventional approach.

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Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei. 2015-06-10. Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems. https://doi.org/10.1109/aspdac.2015.7059045

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