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arXiv · 1507.07155

Majority Logic Decoding under Data-Dependent Logic Gate Failures

Srdan Brkic·Predrag Ivanis·Bane Vasic
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Abstract

A majority logic decoder made of unreliable logic gates, whose failures are transient and datadependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for an one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.

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Srdan Brkic, Predrag Ivanis, Bane Vasic. 2015-07-26. Majority Logic Decoding under Data-Dependent Logic Gate Failures. https://arxiv.org/abs/1507.07155

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