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arXiv · 1512.05578

Improving Latency in a Signal Processing System on the Epiphany Architecture

Peter Brauer·Martin Lundqvist·Aare Mällo
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Abstract

In this paper we use the Adapteva Epiphany manycore chip to demonstrate how the throughput and the latency of a baseband signal processing chain, typically found in LTE or WiFi, can be optimized by a combination of task- and data parallelization, and data pipelining. The parallelization and data pipelining are facilitated by the shared memory architecture of the Epiphany, and the fact that a processor on one core can write directly into the memory of any other core on the chip.

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Peter Brauer, Martin Lundqvist, Aare Mällo. 2015-12-17. Improving Latency in a Signal Processing System on the Epiphany Architecture. https://arxiv.org/abs/1512.05578

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