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arXiv · 1609.04567

A parallel pattern for iterative stencil + reduce

M. Aldinucci·M. Danelutto·M. Drocco·P. Kilpatrick·C. Misale·G. Peretti Pezzi·M. Torquati
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Abstract

We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.

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M. Aldinucci, M. Danelutto, M. Drocco, P. Kilpatrick, C. Misale, G. Peretti Pezzi, M. Torquati. 2016-09-15. A parallel pattern for iterative stencil + reduce. https://doi.org/10.1007/s11227-016-1871-z

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