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arXiv · 1712.04166

Weighted p-bits for FPGA implementation of probabilistic circuits

Ahmed Zeeshan Pervaiz·Brian M. Sutton·Lakshmi Anirudh Ghantasala·Kerem Y. Camsari
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Abstract

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware.

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Ahmed Zeeshan Pervaiz, Brian M. Sutton, Lakshmi Anirudh Ghantasala, Kerem Y. Camsari. 2017-12-12. Weighted p-bits for FPGA implementation of probabilistic circuits. https://doi.org/10.1109/tnnls.2018.2874565

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