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arXiv · 1801.09026

Voltage-driven Building Block for Hardware Belief Networks

Orchi Hassan·Kerem Y. Camsari·Supriyo Datta
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Abstract

Probabilistic spin logic (PSL), based on networks of binary stochastic neurons (or p-bits), has been shown to provide a viable framework for many functionalities including Ising computing, Bayesian inference, invertible Boolean logic and image recognition. This paper presents a hardware building block for the PSL architecture, consisting of an embedded MTJ and a capacitive voltage adder of the type used in neuMOS. We use SPICE simulations to show how identical copies of these building blocks (or weighted p-bits) can be interconnected with wires to design and solve a small instance of the NP-complete Subset Sum Problem fully in hardware.

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Orchi Hassan, Kerem Y. Camsari, Supriyo Datta. 2019-02-08. Voltage-driven Building Block for Hardware Belief Networks. https://doi.org/10.1109/mdat.2019.2897964

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