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arXiv · 1807.10695

FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software

Jin Hee Kim·Brett Grady·Ruolong Lian·John Brothers·Jason H. Anderson
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Abstract

A deep-learning inference accelerator is synthesized from a C-language software program parallelized with Pthreads. The software implementation uses the well-known producer/consumer model with parallel threads interconnected by FIFO queues. The LegUp high-level synthesis (HLS) tool synthesizes threads into parallel FPGA hardware, translating software parallelism into spatial parallelism. A complete system is generated where convolution, pooling and padding are realized in the synthesized accelerator, with remaining tasks executing on an embedded ARM processor. The accelerator incorporates reduced precision, and a novel approach for zero-weight-skipping in convolution. On a mid-sized Intel Arria 10 SoC FPGA, peak performance on VGG-16 is 138 effective GOPS.

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Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason H. Anderson. 2018-07-27. FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software. https://doi.org/10.1109/socc.2017.8226056

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