STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction

Abstract

With aggressively shrinking process nodes, physical design methods face severe challenges due to poor convergence and uncertainty in getting an optimal solution. An early detection of potential failures is thus mandated. This has encouraged to devise a feedback mechanism from a lower abstraction level of the design flow to the higher ones, such as placement driven synthesis, routability (timing) driven placement etc. Motivated by this, we propose an early global routing framework using pattern routing following the floorplanning stage. We assess feasibility of a floorplan topology of a given design by estimating routability, routed wirelength and vias count while addressing the global congestion scenario across the layout. Different capacity profiles for the routing regions, such as uniform or non-uniform different cases of metal pitch variation across the metals layers ensures adaptability to technology scaling. The proposed algorithm STAIRoute takes $O(n^2kt)$ time for a given design with $n$ blocks and $k$ nets having at most $t$ terminals. Experimental results on a set of floorplanning benchmark circuits show $100\%$ routing completion, with no over-congestion in the routing regions reported. The wirelength for the $t$-terminal ($t\geq$ 2) nets is comparable with the Steiner length computed by FLUTE. An estimation on the number of vias for different capacity profiles is also presented, along with congestion and runtime results.