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arXiv · 1901.04989

Application-Specific System Processor for the SHA-1 Hash Algorithm

Carlos E. B. S. Júnior·Matheus F. Torquato·Marcelo A. C. Fernandes
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Abstract

This work proposes an Application-Specific System Processor (ASSP) hardware for the Secure Hash Algorithm 1 (SHA-1) algorithm. The proposed hardware was implemented in a Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. The throughput and the occupied area were analyzed for several implementations in parallel instances of the hash algorithm. The results showed that the hardware proposed for the SHA-1 achieved a throughput of 0.644 Gbps for a single instance and slightly more than 28 Gbps for 48 instances in a single FPGA. Various applications such as password recovery, password validation, and high volume data integrity checking can be performed efficiently and quickly with an ASSP for SHA1.

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BibTeXRIS

Carlos E. B. S. Júnior, Matheus F. Torquato, Marcelo A. C. Fernandes. 2018-12-10. Application-Specific System Processor for the SHA-1 Hash Algorithm. https://arxiv.org/abs/1901.04989

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