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arXiv · 1904.02327

An Asymmetric Adaptive SCL Decoder Hardware for Ultra-Low-Error-Rate Polar Codes

Jiajie Tong·Huazi Zhang·Lingchen Huang·Xiaocheng Liu·Jun Wang
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Abstract

In theory, Polar codes do not exhibit an error floor under successive-cancellation (SC) decoding. In practice, frame error rate (FER) down to $10^{-12}$ has not been reported with a real SC list (SCL) decoder hardware. This paper presents an asymmetric adaptive SCL (A2SCL) decoder, implemented in real hardware, for high-throughput and ultra-reliable communications. We propose to concatenate multiple SC decoders with an SCL decoder, in which the numbers of SC/SCL decoders are balanced with respect to their area and latency. In addition, a novel unequal-quantization technique is adopted. The two optimizations are crucial for improving SCL throughput within limited chip area. As an application, we build a link-level FPGA emulation platform to measure ultra-low FERs of 3GPP NR Polar codes (with parity-check and CRC bits). It is flexible to support all list sizes up to $8$, code lengths up to $1024$ and arbitrary code rates. With the proposed hardware, decoding speed is 7000 times faster than a CPU core. For the first time, FER as low as $10^{-12}$ is measured and quantization effect is analyzed.

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Jiajie Tong, Huazi Zhang, Lingchen Huang, Xiaocheng Liu, Jun Wang. 2019-04-04. An Asymmetric Adaptive SCL Decoder Hardware for Ultra-Low-Error-Rate Polar Codes. https://arxiv.org/abs/1904.02327

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