Simulating collective neutrinos oscillations on the Intel Many Integrated Core (MIC) architecture

Vahid Noormofidi; Susan R. Atlas; Huaiyu Duan

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arXiv · 1912.10596

Simulating collective neutrinos oscillations on the Intel Many Integrated Core (MIC) architecture

Vahid Noormofidi·Susan R. Atlas·Huaiyu Duan

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Abstract

We evaluate the second-generation Intel Xeon Phi coprocessor based on the Intel Many Integrated Core (MIC) architecture, aka the Knights Landing or KNL, for simulating neutrino oscillations in (core-collapse) supernovae. For this purpose we have developed a numerical code XFLAT which is optimized for the MIC architecture and which can run on both the homogeneous HPC platform with CPUs or Xeon Phis only and the hybrid platform with both CPUs and Xeon Phis. To efficiently utilize the SIMD (vector) units of the MIC architecture we implemented a design of Structure of Array (SoA) in the low-level module of the code. We benchmarked the code on the NERSC Cori supercomputer which is equipped with dual 68-core 7250 Xeon Phis. We find that compare to the first generation of the Xeon Phi (Knights Corner a.k.a KNC) the performance improves by many folds. Some of the problems that we encountered in this work may be solved with the advent of the new supernova model for neutrino oscillations and the next-generation Xeon Phi.

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BibTeX RIS

Vahid Noormofidi, Susan R. Atlas, Huaiyu Duan. 2019-12-23. Simulating collective neutrinos oscillations on the Intel Many Integrated Core (MIC) architecture. https://arxiv.org/abs/1912.10596

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