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arXiv · 2001.05463

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests

Lizhou Wu·Mottaqiallah Taouil·Siddharth Rao·Erik Jan Marinissen·Said Hamdioui
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Abstract

As one of the most promising emerging non-volatile memory (NVM) technologies, spin-transfer torque magnetic random access memory (STT-MRAM) has attracted significant research attention due to several features such as high density, zero standby leakage, and nearly unlimited endurance. However, a high-quality test solution is required prior to the commercialization of STT-MRAM. In this paper, we present all STT-MRAM failure mechanisms: manufacturing defects, extreme process variations, magnetic coupling, STT-switching stochasticity, and thermal fluctuation. The resultant fault models including permanent faults and transient faults are classified and discussed. Moreover, the limited test algorithms and design-for-testability (DfT) designs proposed in the literature are also covered. It is clear that test solutions for STT-MRAMs are far from well established yet, especially when considering a defective part per billion (DPPB) level requirement. We present the main challenges on the STT-MRAM testing topic at three levels: failure mechanisms, fault modeling, and test/DfT designs.

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Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui. 2020-01-15. Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. https://arxiv.org/abs/2001.05463

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