A 75kb SRAM in 65nm CMOS for In-Memory Computing Based Neuromorphic Image Denoising

Sumon Kumar Bose; Vivek Mohan; Arindam Basu

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arXiv · 2003.10300

A 75kb SRAM in 65nm CMOS for In-Memory Computing Based Neuromorphic Image Denoising

Sumon Kumar Bose·Vivek Mohan·Arindam Basu

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Abstract

This paper presents an in-memory computing (IMC) architecture for image denoising. The proposed SRAM based in-memory processing framework works in tandem with approximate computing on a binary image generated from neuromorphic vision sensors. Implemented in TSMC 65nm process, the proposed architecture enables approximately 2000X energy savings (approximately 222X from IMC) compared to a digital implementation when tested with the video recordings from a DAVIS sensor and achieves a peak throughput of 1.25-1.66 frames/us.

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Sumon Kumar Bose, Vivek Mohan, Arindam Basu. 2020-03-23. A 75kb SRAM in 65nm CMOS for In-Memory Computing Based Neuromorphic Image Denoising. https://arxiv.org/abs/2003.10300

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