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arXiv · 2004.04852

Predictable Accelerator Design with Time-Sensitive Affine Types

Rachit Nigam·Sachille Atapattu·Samuel Thomas·Zhijing Li·Theodore Bauer·Yuwei Ye·Apurva Koti·Adrian Sampson·Zhiru Zhang
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Abstract

Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs. Repurposing legacy software languages, however, requires complex heuristics to map imperative code onto hardware structures. We find that the black-box heuristics in HLS can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger designs. This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators. The key idea is to model consumable hardware resources with a time-sensitive affine type system that prevents simultaneous uses of the same hardware structure. We implement the type system in Dahlia, a language that compiles to HLS C++, and show that it can reduce the size of HLS parameter spaces while accepting Pareto-optimal designs.

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Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang. 2020-04-09. Predictable Accelerator Design with Time-Sensitive Affine Types. https://doi.org/10.1145/3395657

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