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arXiv · 2005.11357

Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation

Xuan Guo·Robert Mullins
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Abstract

It has always been difficult to balance the accuracy and performance of ISSs. RTL simulators or systems such as gem5 are used to execute programs in a cycle-accurate manner but are often prohibitively slow. In contrast, functional simulators such as QEMU can run large benchmarks to completion in a reasonable time yet capture few performance metrics and fail to model complex interactions between multiple cores. This paper presents a novel multi-purpose simulator that exploits binary translation to offer fast cycle-level full-system simulations. Its functional simulation mode outperforms QEMU and, if desired, it is possible to switch between functional and timing modes at run-time. Cycle-level simulations of RISC-V multi-core processors are possible at more than 20 MIPS, a useful middle ground in terms of accuracy and performance with simulation speeds nearly 100 times those of more detailed cycle-accurate models.

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Xuan Guo, Robert Mullins. 2020-05-22. Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation. https://arxiv.org/abs/2005.11357

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