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arXiv · 2009.01441

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

Zhe Lin·Sharad Sinha·Hao Liang·Liang Feng·Wei Zhang
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Abstract

Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power walls. In this trend, FPGA-based accelerators are becoming increasingly attractive, due to their excellent flexibility and low design cost. In this paper, we propose the architectural support for efficient interfacing between FPGA-based multi-accelerators and chip-multiprocessors (CMPs) connected through the network-on-chip (NoC). Distributed packet receivers and hierarchical packet senders are designed to maintain scalability and reduce the critical path delay under a heavy task load. A dedicated accelerator chaining mechanism is also proposed to facilitate intra-FPGA data reuse among accelerators to circumvent prohibitive communication overhead between the FPGA and processors. In order to evaluate the proposed architecture, a complete system emulation with programmability support is performed using FPGA prototyping. Experimental results demonstrate that the proposed architecture has high-performance, and is light-weight and scalable in characteristics.

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Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang. 2020-09-03. Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. https://doi.org/10.1109/tmscs.2017.2754378

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