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arXiv · 2102.07511

GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent

Heesu Kim·Hanmin Park·Taehyun Kim·Kwanheum Cho·Eojin Lee·Soojung Ryu·Hyuk-Jae Lee·Kiyoung Choi·Jinho Lee
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Abstract

In this paper, we present GradPIM, a processing-in-memory architecture which accelerates parameter updates of deep neural networks training. As one of processing-in-memory techniques that could be realized in the near future, we propose an incremental, simple architectural design that does not invade the existing memory protocol. Extending DDR4 SDRAM to utilize bank-group parallelism makes our operation designs in processing-in-memory (PIM) module efficient in terms of hardware cost and performance. Our experimental results show that the proposed architecture can improve the performance of DNN training and greatly reduce memory bandwidth requirement while posing only a minimal amount of overhead to the protocol and DRAM area.

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Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee. 2021-02-15. GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. https://arxiv.org/abs/2102.07511

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