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arXiv · 2112.07019

Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators

Lennart Bamberg·Arash Pourtaherian·Luc Waeijen·Anupam Chahar·Orlando Moreira
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Abstract

Manufacturing-viable neuromorphic chips require novel computer architectures to achieve the massively parallel and efficient information processing the brain supports so effortlessly. Emerging event-based architectures are making this dream a reality. However, the large memory requirements for synaptic connectivity are a showstopper for the execution of modern convolutional neural networks (CNNs) on massively parallel, event-based (spiking) architectures. This work overcomes this roadblock by contributing a lightweight hardware scheme to compress the synaptic memory requirements by several thousand times, enabling the execution of complex CNNs on a single chip of small form factor. A silicon implementation in a 12-nm technology shows that the technique increases the system's implementation cost by only 2%, despite achieving a total memory-footprint reduction of up to 374x compared to the best previously published technique.

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Lennart Bamberg, Arash Pourtaherian, Luc Waeijen, Anupam Chahar, Orlando Moreira. 2021-12-13. Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators. https://arxiv.org/abs/2112.07019

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