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arXiv · 2203.06117

GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement

Yanqing Zhang·Haoxing Ren·Akshay Sridharan·Brucek Khailany
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Abstract

In this paper, we present GATSPI, a novel GPU accelerated logic gate simulator that enables ultra-fast power estimation for industry sized ASIC designs with millions of gates. GATSPI is written in PyTorch with custom CUDA kernels for ease of coding and maintainability. It achieves simulation kernel speedup of up to 1668X on a single-GPU system and up to 7412X on a multiple-GPU system when compared to a commercial gate-level simulator running on a single CPU core. GATSPI supports a range of simple to complex cell types from an industry standard cell library and SDF conditional delay statements without requiring prior calibration runs and produces industry-standard SAIF files from delay-aware gate-level simulation. Finally, we deploy GATSPI in a glitch-optimization flow, achieving a 1.4% power saving with a 449X speedup in turnaround time compared to a similar flow using a commercial simulator.

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Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany. 2022-03-11. GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement. https://arxiv.org/abs/2203.06117

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