Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks

Dhandeep Challagundla; Mehedi Galib; Ignatius Bezzam; Riadul Islam

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arXiv · 2205.07949

Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks

Dhandeep Challagundla·Mehedi Galib·Ignatius Bezzam·Riadul Islam

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Abstract

As the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and inductor matching technique to address this bottleneck. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor matching technique aids in reducing the skew, increasing the robustness of the clock network. This new resonant architecture saves over 43% power and 91% skew clocking a range of 1--5 GHz, compared to a conventional primary-secondary flip-flop-based CMOS architecture.

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Dhandeep Challagundla, Mehedi Galib, Ignatius Bezzam, Riadul Islam. 2022-05-16. Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks. https://arxiv.org/abs/2205.07949

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