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arXiv · 2208.11208

Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform

Yuan Meng·Rajgopal Kannan·Viktor Prasanna
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Abstract

Monte Carlo Tree Search (MCTS) methods have achieved great success in many Artificial Intelligence (AI) benchmarks. The in-tree operations become a critical performance bottleneck in realizing parallel MCTS on CPUs. In this work, we develop a scalable CPU-FPGA system for Tree-Parallel MCTS. We propose a novel decomposition and mapping of MCTS data structure and computation onto CPU and FPGA to reduce communication and coordination. High scalability of our system is achieved by encapsulating in-tree operations in an SRAM-based FPGA accelerator. To lower the high data access latency and inter-worker synchronization overheads, we develop several hardware optimizations. We show that by using our accelerator, we obtain up to $35\times$ speedup for in-tree operations, and $3\times$ higher overall system throughput. Our CPU-FPGA system also achieves superior scalability wrt number of parallel workers than state-of-the-art parallel MCTS implementations on CPU.

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Yuan Meng, Rajgopal Kannan, Viktor Prasanna. 2022-08-23. Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform. https://arxiv.org/abs/2208.11208

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