Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems

Maryam Babaie; Ayaz Akram; Jason Lowe-Power

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arXiv · 2303.13029

Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems

Maryam Babaie·Ayaz Akram·Jason Lowe-Power

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Abstract

The increasing growth of applications' memory capacity and performance demands has led the CPU vendors to deploy heterogeneous memory systems either within a single system or via disaggregation. For instance, systems like Intel's Knights Landing and Sapphire Rapids can be configured to use high bandwidth memory as a cache to main memory. While there is significant research investigating the designs of DRAM caches, there has been little research investigating DRAM caches from a full system point of view, because there is not a suitable model available to the community to accurately study largescale systems with DRAM caches at a cycle-level. In this work we describe a new cycle-level DRAM cache model in the gem5 simulator which can be used for heterogeneous and disaggregated systems. We believe this model enables the community to perform a design space exploration for future generation of memory systems supporting DRAM caches.

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Maryam Babaie, Ayaz Akram, Jason Lowe-Power. 2023-03-23. Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems. https://arxiv.org/abs/2303.13029

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