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arXiv · 2304.01756

Comparing planar quantum computing platforms at the quantum speed limit

Daniel Basilewitsch·Clemens Dlaska·Wolfgang Lechner
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Abstract

An important aspect that strongly impacts the experimental feasibility of quantum circuits is the ratio of gate times and typical error time scales. Algorithms with circuit depths that significantly exceed the error time scales will result in faulty quantum states and error correction is inevitable. We present a comparison of the theoretical minimal gate time, i.e., the quantum speed limit (QSL), for realistic two- and multi-qubit gate implementations in neutral atoms and superconducting qubits. Subsequent to finding the QSLs for individual gates by means of optimal control theory we use them to quantify the circuit QSL of the quantum Fourier transform and the quantum approximate optimization algorithm. In particular, we analyze these quantum algorithms in terms of circuit run times and gate counts both in the standard gate model and the parity mapping. We find that neutral atom and superconducting qubit platforms show comparable weighted circuit QSLs with respect to the system size.

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Daniel Basilewitsch, Clemens Dlaska, Wolfgang Lechner. 2023-04-04. Comparing planar quantum computing platforms at the quantum speed limit. https://doi.org/10.1103/physrevresearch.6.023026

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