SearcharxivSearch

arXiv · 2305.03165

Understanding the Benefits of Hardware-Accelerated Communication in Model-Serving Applications

Abstract

It is commonly assumed that the end-to-end networking performance of edge offloading is purely dictated by that of the network connectivity between end devices and edge computing facilities, where ongoing innovation in 5G/6G networking can help. However, with the growing complexity of edge-offloaded computation and dynamic load balancing requirements, an offloaded task often goes through a multi-stage pipeline that spans across multiple compute nodes and proxies interconnected via a dedicated network fabric within a given edge computing facility. As the latest hardware-accelerated transport technologies such as RDMA and GPUDirect RDMA are adopted to build such network fabric, there is a need for good understanding of the full potential of these technologies in the context of computation offload and the effect of different factors such as GPU scheduling and characteristics of computation on the net performance gain achievable by these technologies. This paper unveils detailed insights into the latency overhead in typical machine learning (ML)-based computation pipelines and analyzes the potential benefits of adopting hardware-accelerated communication. To this end, we build a model-serving framework that supports various communication mechanisms. Using the framework, we identify performance bottlenecks in state-of-the-art model-serving pipelines and show how hardware-accelerated communication can alleviate them. For example, we show that GPUDirect RDMA can save 15--50\% of model-serving latency, which amounts to 70--160 ms.

Explore related subjects

Keep this discovery

BibTeXRIS

Walid A. Hanafy, Limin Wang, Hyunseok Chang, Sarit Mukherjee, T. V. Lakshman, Prashant Shenoy. 2023-05-04. Understanding the Benefits of Hardware-Accelerated Communication in Model-Serving Applications. https://arxiv.org/abs/2305.03165

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

PASCAL: A Phase-Aware Shared-Cache Model for Parallel Scans

In modern AI Accelerators and GPGPUs, many concurrent cores repeatedly access the same shared data. This pattern occurs in attention, where different query tiles share the same K/V block, GEMM, where every tile in a row reads the same panel, and many other operators. We name this pattern parallel scan. Due to a significant amount of data reuse in this pattern, the cache is expected to capture as much data reuse as possible and largely reduce requests sent to the main memory for both performance and energy consumption concerns. However, in reality, because of the intrinsic asynchrony of multi-cores, the actual cache miss rate and DRAM traffic can be much higher compared to ideal cases. In this paper, we propose PASCAL, a shared-cache model for parallel scans. It is aware of the dynamic feature of progress divergence across multi-cores, correlate the divergence with the combination of different factors such as occupancy, and predicts the cache miss rate before execution. Because prediction needs no target trace, timing, or counters, PASCAL supports design-space exploration at scales where cycle-accurate simulation is impractical, and its policy-independent bound states how much traffic no replacement policy can avoid. A MAPE of 13.84% is achieved in a 60-configuration dataset with various software pipeline depths, occupancies, and memory access data paths on an NVIDIA GB10 GPU, against 44.79% for physical-wave TileSight and 54.16% for exact symbolic SDCM.

cs.PF

Mathematical Modeling of a Cognitive Continuum Digital Shadow for Large-Scale, Cross-Facility Workflows

We present the mathematical foundations of a \emph{Cognitive Continuum Digital Shadow} (CCDS), a decision-support layer between users and the cross-facility infrastructure---instruments, networks, data stores and compute centers---of exascale and post-exascale scientific workflows. The CCDS couples a state-space representation of the continuum with multistage stochastic programming, so that deployment scenarios can be explored and optimized \emph{before} jobs are launched. This allows operators and users to quantify the cost, makespan and energy trade-offs of a workflow under uncertain resource availability, and hedge their decisions accordingly. We formulate the underlying optimization as a multimode, resource-constrained, stochastic supply-chain network design problem and demonstrate it on a realistic genomics workflow scheduled across heterogeneous HPC and data-center resources. This is the first of three papers; the second treats the underlying software architecture and the third reports large-scale use-cases.

cs.PF

RGB Input Pipelines: Throughput, GPU Memory, and Transformation Coverage

An image-augmentation pipeline must deliver a complete batch before a model can use it. We compare seven input paths from five libraries, starting with RGB JPEG files and ending with a synchronized CUDA float16 batch. We manually matched transformation recipes and parameters across libraries to make the workloads as comparable as possible. The experiment uses 57 selected recipes, a batch size of 256, and one NVIDIA L4 machine. Throughput and peak process GPU memory are recorded together in 759 measurements. On the 11 recipes shared by all paths, DALI and AlbumentationsX have median throughputs of 5,029 and 4,679 images/s, with median peak GPU memory of 2,086 and 1,852 MiB. Broader pairwise comparisons favor AlbumentationsX on 26/26 TorchVision recipes, 50/51 Kornia recipes, and 25/26 Pillow recipes. DALI is faster than AlbumentationsX on all 22 shared recipes, with a median throughput ratio of 1.18x. A separate census reports coverage of the 118 entries in a selected AlbumentationsX RGB catalog. The study measures input preparation at fixed settings; it does not measure model training, numerical equivalence, or the best attainable configuration of each library. Benchmark code: https://github.com/albumentations-team/benchmark.

cs.PF