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arXiv · 2309.12864

The Importance of Worst-Case Memory Contention Analysis for Heterogeneous SoCs

Lorenzo Carletti·Gianluca Brilli·Alessandro Capotondi·Paolo Valente·Andrea Marongiu
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Abstract

Memory interference may heavily inflate task execution times in Heterogeneous Systems-on-Chips (HeSoCs). Knowing worst-case interference is consequently fundamental for supporting the correct execution of time-sensitive applications. In most of the literature, worst-case interference is assumed to be generated by, and therefore is estimated through read-intensive synthetic workloads with no caching. Yet these workloads do not always generate worst-case interference. This is the consequence of the general results reported in this work. By testing on multiple architectures, we determined that the highest interference generation traffic pattern is actually hardware dependant, and that making assumptions could lead to a severe underestimation of the worst-case (in our case, of more than 9x).

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Lorenzo Carletti, Gianluca Brilli, Alessandro Capotondi, Paolo Valente, Andrea Marongiu. 2023-09-22. The Importance of Worst-Case Memory Contention Analysis for Heterogeneous SoCs. https://arxiv.org/abs/2309.12864

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