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arXiv · 2310.09094

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Heiner Bauer·Marco Stolba·Stefan Scholze·Dennis Walter·Christian Mayr·Alexander Oefelein·Sebastian Höppner·André Scharfe·Flo Schraut·Holger Eisenreich
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Abstract

We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by using an adaptive reverse body biasing aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from -40 {\deg}C to 125 {\deg}C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.

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Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Flo Schraut, Holger Eisenreich. 2023-10-13. A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. https://doi.org/10.1109/isocc59558.2023.10396509

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