Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs

Shivam Aggarwal; Hans Jakob Damsgaard; Alessandro Pappalardo; Giuseppe Franco; Thomas B. Preußer; Michaela Blott; Tulika Mitra

arXiv · 2311.12359

Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs

Shivam Aggarwal·Hans Jakob Damsgaard·Alessandro Pappalardo·Giuseppe Franco·Thomas B. Preußer·Michaela Blott·Tulika Mitra

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Abstract

Post-training quantization (PTQ) is a powerful technique for model compression, reducing the numerical precision in neural networks without additional training overhead. Recent works have investigated adopting 8-bit floating-point formats(FP8) in the context of PTQ for model inference. However, floating-point formats smaller than 8 bits and their relative comparison in terms of accuracy-hardware cost with integers remains unexplored on FPGAs. In this work, we present minifloats, which are reduced-precision floating-point formats capable of further reducing the memory footprint, latency, and energy cost of a model while approaching full-precision model accuracy. We implement a custom FPGA-based multiply-accumulate operator library and explore the vast design space, comparing minifloat and integer representations across 3 to 8 bits for both weights and activations. We also examine the applicability of various integerbased quantization techniques to minifloats. Our experiments show that minifloats offer a promising alternative for emerging workloads such as vision transformers.

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BibTeX RIS

Shivam Aggarwal, Hans Jakob Damsgaard, Alessandro Pappalardo, Giuseppe Franco, Thomas B. Preußer, Michaela Blott, Tulika Mitra. 2023-11-21. Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs. https://arxiv.org/abs/2311.12359

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