32-Bit RISC-V CPU Core on Logisim

Siddesh D. Patil; Premraj V. Jadhav; Siddharth Sankhe

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arXiv · 2312.01455

32-Bit RISC-V CPU Core on Logisim

Siddesh D. Patil·Premraj V. Jadhav·Siddharth Sankhe

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Abstract

This project focuses on making a RISC-V CPU Core using the Logisim software. RISC-V is significant because it will allow smaller device manufacturers to build hardware without paying royalties and allow developers and researchers to design and experiment with a proven and freely available instruction set architecture. RISC-V is ideal for a variety of applications from IOTs to Embedded systems such as disks, CPUs, Calculators, SOCs, etc. RISC-V(Reduced Instruction Set Architecture) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.

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BibTeX RIS

Siddesh D. Patil, Premraj V. Jadhav, Siddharth Sankhe. 2023-12-03. 32-Bit RISC-V CPU Core on Logisim. https://arxiv.org/abs/2312.01455

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