FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning

Shang Wang; Deepak Ranganatha Sastry Mamillapalli; Tianpei Yang; Matthew E. Taylor

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arXiv · 2404.13061

FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning

Shang Wang·Deepak Ranganatha Sastry Mamillapalli·Tianpei Yang·Matthew E. Taylor

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Abstract

This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning (RL) with the goal of minimizing wirelength. In addition to our preliminary learning results, we also evaluated a novel decomposition to address the nature of large search space when placing many blocks on a chipboard. Empirical experiments evaluate the effectiveness of the learning and decomposition paradigms on FPGA placement tasks.

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BibTeX RIS

Shang Wang, Deepak Ranganatha Sastry Mamillapalli, Tianpei Yang, Matthew E. Taylor. 2024-04-11. FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning. https://arxiv.org/abs/2404.13061

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