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arXiv · 2404.19246

Logistic Map Pseudo Random Number Generator in FPGA

Mateo Jalen Andrew Calderon·Lee Jun Lei Lucas·Syarifuddin Azhar Bin Rosli·Stephanie See Hui Ying·Jarell Lim En Yu·Maoyang Xiang·T. Hui Teo
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Abstract

This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem (CLT) function to achieve a Gaussian distribution. The system integrates additional FPGA modules for real-time interaction and visualisation, including a clock generator, UART interface, XADC, and a 7-segment display driver. These components facilitate the direct display of PRNG values on the FPGA and the transmission of data to a laptop for histogram analysis, verifying the Gaussian nature of the output. This approach demonstrates the practical application of chaotic systems for generating Gaussian-distributed pseudo-random numbers in digital hardware, highlighting the logistic map's potential in PRNG design.

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Mateo Jalen Andrew Calderon, Lee Jun Lei Lucas, Syarifuddin Azhar Bin Rosli, Stephanie See Hui Ying, Jarell Lim En Yu, Maoyang Xiang, T. Hui Teo. 2024-04-30. Logistic Map Pseudo Random Number Generator in FPGA. https://doi.org/10.1109/mcsoc64144.2024.00035

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