Micro-orchestration of RAN functions accelerated in FPGA SoC devices

Nikolaos Bartzoudis; José Rubio Fernández; David López-Bueno; Godfrey Kibalya; Angelos Antonopoulos

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arXiv · 2409.11362

Micro-orchestration of RAN functions accelerated in FPGA SoC devices

Nikolaos Bartzoudis·José Rubio Fernández·David López-Bueno·Godfrey Kibalya·Angelos Antonopoulos

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Abstract

This work provides a vision on how to tackle the underutilization of compute resources in FPGA SoC devices used across 5G and edge computing infrastructures. A first step towards this end is the implementation of a resource management layer able to migrate and scale functions in such devices, based on context events. This layer sets the basis to design a hierarchical data-driven micro-orchestrator in charge of providing the lifecycle management of functions in FPGA SoC devices. In the O-RAN context, the micro-orchestrator is foreseen to take the form of an xApp/rApp tandem trained with RAN traffic and context data.

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Nikolaos Bartzoudis, José Rubio Fernández, David López-Bueno, Godfrey Kibalya, Angelos Antonopoulos. 2024-09-17. Micro-orchestration of RAN functions accelerated in FPGA SoC devices. https://arxiv.org/abs/2409.11362

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