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arXiv · 2411.19308

Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair

Yuchen Zhu·Jinglei Cheng·Boxi Li·Yidong Zhou·Yufei Ding·Zhiding Liang
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Abstract

In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences among physical qubits and lack efficient parallel calibration. In this paper, we enlarge the pulse candidates for two-qubit gates to three pulse waveforms, and introduce a fine-grained calibration protocol. In the calibration protocol, three policies are proposed to profile each qubit pair with its optimal pulse waveform. Afterwards, calibration subgraphs are introduced to enable parallel calibraton through identifying compatible calibration operations. The protocol is validated on real machine with up to 127 qubits. Real-machine experiments demonstrates a minimum gate error of 0.001 with a median error of 0.006 which is 1.84x reduction compared to default pulse waveform provided by IBM. On device level, a double fold increase in quantum volume as well as 2.3x reduction in error per layered gate are achieved. The proposed protocol leverages the potential current hardware and could server as an important step toward fault-tolerant quantum computing.

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Yuchen Zhu, Jinglei Cheng, Boxi Li, Yidong Zhou, Yufei Ding, Zhiding Liang. 2024-11-28. Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair. https://arxiv.org/abs/2411.19308

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