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arXiv · 2412.20161

Multi Ratio Shift Keying (MRSK) for Molecular Communication

Abstract

Molecular Communication (MC) leverages the power of diffusion to transmit molecules from a transmitter to a receiver. A wide variety of modulation techniques based on molecule concentration, type, and release time have been extensively studied in the literature. In this paper, we propose a novel modulation technique that encodes the information into the relative concentrations of multiple molecules called Multi Ratio Shift Keying (MRSK) designed for diffusion-based MC without drift. We show that leveraging all possible ratios in a set of molecules can help mitigate the effects of intersymbol interference (ISI) and provide a flexible communication channel. To evaluate the performance of the MRSK, we develop a mathematical framework for studying the statistics of the ratio of random variables, focusing on noncentral Gaussian distributions. We then assess MRSK performance both analytically and through particle-based simulations under various channel conditions, identifying potential sources of error in our system model. Additionally, we conduct a comparative analysis of commonly used modulation schemes in the literature based on bit error rate (BER). The results show that MRSK significantly outperforms all traditional modulation schemes considered in this study in terms of BER. MRSK offers a promising, flexible, and more reliable communication method for the future of the MC paradigm.

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BibTeXRIS

Boran A. Kilic, Ozgur B. Akan. 2024-12-28. Multi Ratio Shift Keying (MRSK) for Molecular Communication. https://arxiv.org/abs/2412.20161

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