Simulation on the Miniaturization and Performance Improvement Study of Gr/MoS2 Based Vertical Field Effect Transistor

Sirsendu Ghosh; Anamika Devi Laishram; Pramod Kumar

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arXiv · 2501.03541

Simulation on the Miniaturization and Performance Improvement Study of Gr/MoS2 Based Vertical Field Effect Transistor

Sirsendu Ghosh·Anamika Devi Laishram·Pramod Kumar

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Abstract

Vertical field effect transistors (VFETs) show many advantages such as high switching speed, low operating voltage, low power consumption, and miniaturization over lateral FETs. However, VFET still faces the main challenges of high off-state current. Graphene (Gr) and transition metal di-chalcogenides (TMDs) are attractive materials for the next generation electronics. In this simulation work, the bulk molybdenum disulfide (MoS2) is sandwiched between perforated monolayer Gr which acts as the source electrode, and aluminum (Al) as the top drain electrode. In addition to this, the minimization of the off-state current is carried out by modifications in the source contact geometry by insulating some part of the source electrode and introducing the extra MoS2 layer between the source and gate dielectric named as buried layer. After the modification, the results show an improvement in OFF current, hence the ON/OFF ratio. The highest ON/OFF ratio of 109 is achieved with top side insulated source contact and thinnest buried layer of 02 nm with top and sidewall insulation. These results would support low voltage operation with high switching speed in complete 2D material based VFETs and further miniaturize its geometry.

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Sirsendu Ghosh, Anamika Devi Laishram, Pramod Kumar. 2025-01-07. Simulation on the Miniaturization and Performance Improvement Study of Gr/MoS2 Based Vertical Field Effect Transistor. https://arxiv.org/abs/2501.03541

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