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arXiv · 2501.10702

An RRAM compute-in-memory architecture for high energy-efficient processing of binary matrix-vector multiplication in cryptography

Hao Yue·Yihao Chen·Tianhang Liang·Xiangrui Li·Xin Kong·Zhelong Jiang·Zhigang Li·Gang Chen·Huaxiang Lu
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Abstract

Binary matrix-vector multiplication (BMVM) is a key operation in post-quantum cryptography schemes like the Classic McEliece cryptosystem. Conventional computing architectures incur significant energy efficiency loss due to data movement of large matrices when handling such tasks. Resistive memory (RRAM) non-volatile compute-in-memory (nvCIM) is an ideal technology for high energy-efficient BMVM processing but faces challenges, including signal margin degradation in high input-parallelism arrays due to device non-idealities and high hardware overhead from current readout and XOR operations. This work presents a RRAM nvCIM architecture featuring: 1) 1T1R cells with high-resistive-state compensation modules; and 2) pulsed current-sensing parity checkers. Based on the 180nm process and test results from RRAM devices, the computing accuracy and efficiency of the architecture are verified by simulation. The proposed architecture performs high-precision current accumulation with a maximum MAC value of 10 and achieves an energy efficiency of 1.51TOPS/W, offering approximately 1.62 times improvement compared to an advanced 28nm FPGA platform.

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Hao Yue, Yihao Chen, Tianhang Liang, Xiangrui Li, Xin Kong, Zhelong Jiang, Zhigang Li, Gang Chen, Huaxiang Lu. 2025-01-18. An RRAM compute-in-memory architecture for high energy-efficient processing of binary matrix-vector multiplication in cryptography. https://arxiv.org/abs/2501.10702

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