Fast Thermal-Aware Chiplet Placement Assisted by Surrogate

Abstract

With the advent of the post-Moore era, the 2.5-D advanced package is a promising solution to sustain the development of very large-scale integrated circuits. However, the thermal placement of chiplet, due to the high complexity of thermal simulation, is very challenging. In this paper, a surrogate-assisted simulated annealing algorithm is proposed to simultaneously minimize both the wirelength and the maximum temperature of integrated chips. To alleviate the computational cost of thermal simulation, a radial basis function network is introduced to approximate the thermal field, assisted by which the simulated annealing algorithm converges to the better placement in less time. Numerical results demonstrate that the surrogate-assisted simulated annealing algorithm is competitive to the state-of-the-art thermal placement algorithms of chiplet, suggesting its potential application in the agile design of 2.5D package chip.