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arXiv · 2505.06687

Extend IVerilog to Support Batch RTL Fault Simulation

Jiaping Tang·Jianan Mu·Zizhen Liu·Zhiteng Chao·Jing Ye·Huawei Li
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Abstract

The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure compliance with functional safety standards. In this paper, we extend IVerilog to support batch RTL fault simulation and integrate the event-driven algorithm and the concurrent fault simulation algorithm. Comparative experiments with a state-of-the-art commercial simulator and an open-source RTL fault simulator demonstrate that our simulator achieves a performance improvement of 2.2$\times$ and 3.4$\times$, respectively.

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Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li. 2025-05-10. Extend IVerilog to Support Batch RTL Fault Simulation. https://arxiv.org/abs/2505.06687

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