Automated Formal Verification of Area-Optimized Safety Registers in Automotive SoCs

Abstract

Registers are primary storage elements in System-on-chip~(SoC) designs and play an important role in maintaining state information and processing data in digital systems. With respect to the ISO26262 standard, these registers require high levels of reliability and fault tolerance. For this reason, safety-critical applications require that normal registers are equipped with additional safety components to construct safety registers, which ensure system stability and fault tolerance. However, the process of integrating these safety registers is complex and error-prone, because of highly-configurable features provided by a safety library such as parameterized modules and flexible safety structures. In addition, to address the overhead caused by the safety registers, we have applied area optimization techniques to their implementation. However, this optimization can make the integration process more susceptible to errors. To avoid any integration mistakes, rigorous verification is always required, but it is time-consuming and error-prone if the verification is implemented manually when dealing with numerous verification requests. To address these challenges, we propose an automated flow for the verification of safety registers with the formal approach. The results indicate that this automated verification approach has the potential to reduce the verification effort by more than 80\%. Additionally, it ensures a comprehensive examination of every requirement of this safety library, which is reflected in faster detection of bugs. The proposed framework can be replicated for the verification of other safety components enabling an early detection of potential issues and saving valuable time and resources.